BE and FE requirements

Role

Mandatory skills

Location

DFT
(4 to 8yrs & 10-20Yrs)

Bangalore / Hyderabad (3+yrs works too)

>JTAG

>ATPG

>MBIST

>SCAN

STA(6+/10+Yrs)

> SDC and constraints syntax

Bangalore

>Timing signoff tools like Primetime / Tempus is a must

>MMMC, DMSA or Tweaker

>Block /SOC,AOCV/POCV, TCL / Perl.

SoC level – Synthesis and Power Analysis Engineer

SoC level – Synthesis and Power Analysis Engineer
Experience : 8+ years of relevant experience
Expectations:·         
Develop and implement high-performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools.·         
Work closely with design teams to understand the requirements and constraints of the design, and provide feedback on design feasibility, timing and power.·        
Debug and resolve design issues related to synthesis, timing, power, and area.·         
Understanding of DFT flows, including scan insertion and ATPG.·         
Optimize designs for power, performance, and area, and meet design goals within the given schedule.·         
Perform power analysis and optimize designs for low power.·         
Proficient with EDA tools from Synopsys/Cadence/Mentor.·         
Excellent analytical & communication skills.·         
Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone.·         
Proficient in Tcl and Perl or other scripting relevant language is a plus.

Bangalore

Memory Char (5+ Yrs

• Characterization and generation of front end and back end views for standard cell libraries
• Custom cell characterization setup and flows
• Library verification and validation
• Automation for the QA checks, for small tasks in setting up the flows for characterization and QA
• Documentation of and recording the issues, debugs, solutions and new/enhanced work flows

Bangalore

Reqs

Experience & Skillset

Location

Priority

DV- PCIe

senior DV Engineer ( 6+/ 8+ Yrs) for IP/ Subsystem level work (Individual contributor).

Expected skillsets are :

Coding hands on SV/UVM
Can work independently on tasks such code UVM/SV based components/relevant logic, testcase development
Can debug test failures and root cause issue independently in complex design.
Have exposure to PCIe and AXI
Good reasoning and communication skills
Must have strong knowledge in PCIe Gen1/3/4/5 (Logical PHY, LTSSM, DLL & TL)
Must have hands-on debugging skills with both log files and waveform. Prior experience on 3rd party test suite is added advantage.
Must have SV knowledge like writing Constraints, Assertions, Functional coverage etc.
Capable of understanding complex Test benches in a given time.
Good to have RAL understanding

Bangalore

P1

FPGA RTL Design Integration

RTL Integration- 6+yrs
Excellent scripting expertise
Integration tools
Altera Tools

Bangalore

P1

AMS Verification

What will you be doing in this role? (Responsibilities)

Experience: 4 to 10yrs

Verification of complex analog designs/systems, support validation of the design on silicon.
High quality, timely release of meticulously analyzed and simulated IC designs. These designs should lead to best performance, cost-effective, high quality, bug-free products that fully meet our customer’s end system requirements.
Definition, specification, modeling, planning, and implementation of AMS verification strategy for mixed signal ICs (70%+ Analog). Implementation and debug of AMS verification environments, regression testing, reporting of results and coverage analysis.
Write detailed verification plans to cover project requirements for top-level AMS functionality, and construct test cases exercising the plan.
Evaluate system-level use-cases and re-create these in simulation.
Enable high-quality verification through efficient use of bug tracking tools and methods, including back-annotation of DV implementation into the verification plan to show closure of functional requirements.
Planning, leading, and tracking of design & verification projects in a global organization.
Post layout parasitic extraction and simulation, verification of all IC level performance metrics.
Contribute to continuous improvements for quality and efficiency on design verification strategy, tools, methods, and flows.
What do we expect from you? (Mini Qualifications)

Knowledge and Skills

Strong background in defining and developing verification infrastructure for mixed signal semiconductor products.
Good understanding of analog circuits, ability to come up with analog models required.
Expertise in Cadence Virtuoso, Cadence Spectre/TISpice, Verilog-AMS/System Verilog.
Thorough understanding of AMS simulations, digital RTL, analog schematics.
Exposure to supporting post silicon investigations to ensure silicon measurements match pre-silicon verification results.
Proficiency in scripting languages and utilities, including Python, Perl, etc.

Bangalore

P1