| FE | ||
| Requirement | JD | Location |
| DV- PCIE | 5 to 7yrs Must have strong knowledge in PCIe Gen1/3/4/5 (Logical PHY, LTSSM, DLL & TL) Must have hands-on debugging skills with both log files and waveform. Prior experience on 3rd party test suite is added advantage. Must have SV knowledge like writing Constraints, Assertions, Functional coverage etc. Capable of understanding complex Test benches in a given time. Good to have RAL understanding If not PCIe, look for CXL/ UCIe |
Bangalore |
Interested candidates share cv to hr@liafon.com ( please mention job title in the subject line )