What are we looking for?
Competent in Custom Layout Design utilizing Cadence Virtuoso.
Proficient in Hierarchical and Block level Physical aware Synthesis while implementing logical and physical optimization, for timing closure along with deep functional knowledge in ASIC backend design flow including Floor planning, Place and Route, CTS and power analysis flows.
Hands on experience with development of Timing and design constraints.
Familiarity with clock-domain crossing checks along VCLP & PTPX checks.
Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA.
UPF writing, power aware equivalence checks and low power checks.
Hands-on experience in tasks such as LEC, functional ECOs generation and implementation.
Familiarity with ASIC design flows across lower nodes, including 3nm, 7nm, and 14nm nodes.
Capable of simultaneously handling multiple blocks
Strong background in CMOS logic Design fundamentals.
Knowledge and Exposure to Digital System Design using HDL-Verilog.