FE
RequirementJDLocation
DV- PCIE5 to 7yrs
Must have strong knowledge in PCIe Gen1/3/4/5 (Logical PHY, LTSSM, DLL & TL)
Must have hands-on debugging skills with both log files and waveform. Prior experience on 3rd party test suite is added advantage.
Must have SV knowledge like writing Constraints, Assertions, Functional coverage etc.
Capable of understanding complex Test benches in a given time.
Good to have RAL understanding

If not PCIe, look for CXL/ UCIe		Bangalore
BE
RoleMandatory skillsLocation
DFT + ATPGNo of Position-2
Experience : 5 to 8 years.
Skill – ATPG/verification.
Job Description:
Looking for a senior DFT engineer who has hands-on experience in ATPG (SAF, TDF, Bridging Faults), DFT DRC Analysis, Coverage Analysis, GLS verification, Zero-Delay simulations, SDF annotated Simulations. Candidate should have excellent debugging skills to quickly find out the root cause for simulation failures of Timing Simulations. Candidate should be proficient with Synopsys ATPG Tool and Cadence Simulator (Xcelium).
Candidates with GLS verification is preferred.		Imm to 30 days NP.

F2F mandatory;
WFO-5 days;
Bangalore
DFT>JTAG
>ATPG
>MBIST
>SCAN		Bangalore 4+yrs/ Hyderabad (3+yrs works too)
PD- 5 to 10yrsNon-Intel profiles
Innovus + lower technologies (<5mm)/ Samsung foundary		Bangalore (7+yrs)/ Hyderabad (5+yrs)
Memory Char (5+ Yrs• Characterization and generation of front end and back end views for standard cell libraries
• Custom cell characterization setup and flows
• Library verification and validation
• Automation for the QA checks, for small tasks in setting up the flows for characterization and QA
• Documentation of and recording the issues, debugs, solutions and new/enhanced work flows		Bangalore
SoC level – Static timing Analysis EngineerJD: 1SoC level – Static timing Analysis Engineer
Experience: 6+ / 10+ years of relevant experience
Location: Bangalore
Expectations:·         
Candidate should have strong STA fundamentals.·         
Has done timing sign-off including timing margin calculations independently on SoC level.·         
Experience in handling STA of multi-power domain designs.·         
STA flow enhancement, abstraction with bottleneck identification.·         
Proficient in design margins and SDC constructs.·         
TAT reduction in multi-mode, multi power domain/designs.·         
Generate timing ECOs for Physical design.·         
Drive ambitious schedules and enables dependent teams to accomplish.·         
Proficient with EDA tools from Synopsys/Cadence.·         
Excellent analytical & communication skills.·         
Show ability to collaborate in a multi-functional environment, cross-site or cross-time zone.·         
Proficient in Tcl and Perl or other scripting relevant language is a plus.		Bangalore
SoC level – Synthesis and Power Analysis EngineerSoC level – Synthesis and Power Analysis Engineer
Experience : 5+/ 8+ years of relevant experience
Expectations:·         
Develop and implement high-performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools.·         
Work closely with design teams to understand the requirements and constraints of the design, and provide feedback on design feasibility, timing and power.·        
Debug and resolve design issues related to synthesis, timing, power, and area.·         
Understanding of DFT flows, including scan insertion and ATPG.·         
Optimize designs for power, performance, and area, and meet design goals within the given schedule.·         
Perform power analysis and optimize designs for low power.·         
Proficient with EDA tools from Synopsys/Cadence/Mentor.·         
Excellent analytical & communication skills.·         
Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone.·         
Proficient in Tcl and Perl or other scripting relevant language is a plus.		Bangalore
SoC level – Static timing Analysis EngineerExperience : 6+ years of relevant experience
Expectations:·         
Candidate should have strong STA fundamentals.·         
Has done timing sign-off including timing margin calculations independently on SoC level.·         
Experience in handling STA of multi-power domain designs.·         
STA flow enhancement, abstraction with bottleneck identification.·         
Proficient in design margins and SDC constructs.·         
TAT reduction in multi-mode, multi power domain/designs.·         
Generate timing ECOs for Physical design.·        
Drive ambitious schedules and enables dependent teams to accomplish.·         
Proficient with EDA tools from Synopsys/Cadence.·         
Excellent analytical & communication skills.·         
Show ability to collaborate in a multi-functional environment, cross-site or cross-time zone.·         
Proficient in Tcl and Perl or other scripting relevant language is a plus		Bangalore
RoleMandatory skillsLocation
Android BSP Development6 yrs
“Mandatory Skills:
Engineer with 6+ years of experience in Android Framework /HAL/ driver development (2 positions – 6 to 8 Yrs, 2 positions – 8 to 10 Yrs, 2 positions – 10+ Yrs)
Strong C/C++ development skills with a good understanding of object-oriented design
Good understanding of Android framework, overall Android Architecture.
Proficient in any one of Android HAL amongst Audio, Graphics, Camera, Power etc.
Desirable experience with Multimedia framework such as OpenMAX, Codec2.
Compliance to CTS/VTS and support in resolving defects
Strong background in embedded systems development
System knowledge, System Debugging
Keywords: Embedded, Android, HAL, Audio, Video, Camera, Graphics, Framework, OpenMax, Codec2, ALSA, CTS, I2S”		Bangalore
Embedded Linux Development12yrs
“Mandatory Skills:
Engineer with 6+ Yrs of experience in embedded Linux driver/kernel development. (3 positions – 6 to 8 Yrs, 3 positions – 8 to 10 Yrs, 3 positions – 10+ Yrs)
Strong C development skills.
Experience with any one of the driver development domain
Graphics driver – DRM/KMS, OpenGL, Vulkan, OpenCL, Mesa.
Multi Media-Video driver – Vaapi, vdpau, gstreamer, v4l2.
Power management – System to RAM, S0ix3.
Display Driver development – X, Wayland, Weston, Display driver
Experience with Audio sub-system, Audio drivers’s, frameworks and ALSA SOC(ASOC), Audio protocols like I2S/TDM.
Proficient in yocto development.
Virtualization – Xen, KVM, QNX hypervisor knowledge.
Ethernet Driver – Network driver development.
Good working experience with IPC, DMA driver development.
Experience with kernel mode driver programming in Linux
Linux Device driver programming experience in Linux Kernel and Drivers.
Experience dealing with Linux community and Open Source contribution a plus
System knowledge, System Debugging

Keywords: Linux Kernel Driver, device driver, Linux Graphics Driver, DRM/KMS, Video driver, Vaapi, V4L2, Audio DSP, I2S/TDM, Ethernet Driver, Virtualization, Vulkan, Mesa, OpenCL, OpenGL, RTOS”		Bangalore
Audio Development – Linux3 yrs
“1. Engineer with 8+ years of experience in embedded Linux driver/kernel development (2 positions – 8 to 10 Yrs, 1 position: 10+ Yrs)
2. Strong C/C++ development skills with a good understanding of object-oriented design
3. Good understanding of Linux fundamentals and audio fundamentals
4. Experience with ALSA ASoC driver development
5. Experience with audio transmission protocols like I2S/TDM, audio DAC/ADC
6. Experience with audio DSP firmware development
7. Experience with bare metal or RTOS based firmware development
10.System knowledge, System Debugging, firmware debugging using JTAG

Keywords: Linux, Embedded, device driver, RTOS, firmware, ALSA, I2S, ASoC”		Bangalore

Interested candidates share cv to hr@liafon.com ( please mention job title in the subject line )